1. Field of the Invention
The present invention relates to a process for producing a printed wiring board, and particularly to a process for producing a printed wiring board by a so-called full-additive process in which a conductor pattern is additively formed on the surface of an insulating substrate by electroless copper plating.
2. Description of the Prior Art
With the recent development of electronic equipment, electronic components have undergone a significant shift to high density and multifunction, and there is a demand for high-density wiring in printed wiring boards. As a result, a further reduction in line width and line space is required in the printed wiring boards. Under these circumstances, attention is being paid to a process for producing a printed wiring board by additively forming a conductor pattern on the surface of an insulating substrate by electroless copper plating (so-called full-additive process).
A printed wiring board obtained by the full-additive process has a satisfactory dimensional accuracy, as compared with a printed wiring board produced by a conventional process for forming a circuit by plating and etching (subtractive process). Furthermore, the printed wiring board of the circuit of the rectangular section shape obtained by the full-additive process, so that such aboard is suitable for high-density wiring with a narrow line width and space. The dimensional accuracy of a circuit produced by the full-additive process is determined by the dimensional accuracy of a plating resist layer. Therefore, by controlling the dimensional accuracy of the resist layer, a conductive circuit with a high dimensional accuracy can be obtained more easily.
General production steps for a printed wiring board by the full-additive process will be described with reference to FIGS. 1A to 1D. An insulating substrate 102 with an adhesive layer 101 for enhancing plating adhesion formed on the surface of a base substrate 100 such as an epoxy glass substrate or the like is subjected to roughening treatment (FIG. 1A) with a roughening solution such as an alkaline permanganate solution. Then, catalyst cores 103 for electroless copper plating are allowed to adhere to the surface of the roughened adhesive layer 101 (FIG. 1B). Then, regions excluding circuit forming regions are covered with a plating resist 105 having resistance to a plating solution (FIG. 1C). Thereafter, the entire substrate is soaked in an electroless copper plating solution, whereby a copper plating film is deposited on the regions not covered with the plating resist 105 (i.e., circuit forming regions) by electroless copper plating to form conductive circuits 106. Thus, a printed wiring board 200 is produced.
In the case where through-holes are required for allowing both sides of the printed wiring board 200 to have electric conductivity, through-holes 104 are formed before roughening the adhesive layer 101 (FIG. 1B), and the walls of the through-holes 104 are covered with a copper plating film by electroless copper plating simultaneously with the formation of the conductive circuits on the surface of the printed wiring board, whereby copper plated through-holes 107 are formed (FIG. 1D).
However, in the above-mentioned printed wiring board produced by the conventional full-additive process, the plating catalyst cores 103 are present under the plating resist 105. Therefore, when the line space becomes smaller than 100 xcexcm, reliability in electrical insulation between adjacent circuit lines may degrade due to moisture absorption or the like. This is because the catalyst cores present between the lines are ionized with an applied voltage due to moisture absorption and migrate therebetween.
Japanese Patent Application Laid-open No. Sho 62-69696 (hereinafter, referred to as xe2x80x9cfirst prior art techniquexe2x80x9d) discloses a technique of adding silicone oil or fluorine oil to a plating resist so as to improve water repellent of the resist and suppress adsorption of a catalyst solution (palladiumxe2x80x94tin colloid solution) to the resist surface, and selectively forming catalyst cores on the surfaces not covered with the resist (i.e., circuit forming regions). According to this technique, due to water repellent of the plating resist, a catalyst is unlikely to adsorb to the surface of the plating resist. Furthermore, even if a catalyst adsorbs to the surface of the plating resist, the adhesion between the catalyst cores and the plating resist is small, so that the catalyst cores on the plating resist can be easily removed by high-pressure water washing or the like, whereby the insulating property between circuits is enhanced.
Furthermore, Japanese Patent Application Laid-open No. Hei 7-297520 (hereinafter, referred to as xe2x80x9csecond prior art techniquexe2x80x9d) discloses a technique of selectively forming catalyst cores on the surfaces not covered with a plating resist, using a copper metal colloid solution. According to this technique, a plating resist is formed on an insulating substrate, and the resultant insulating substrate is treated with a catalyst solution of a copper metal colloid to allow a copper catalyst to adsorb to the surface of the insulating substrate and the surface of the plating resist. Then, the insulating substrate is treated with an alkaline permanganate solution, whereby the copper catalyst adsorbing to the plating resist is removed. A larger amount of copper catalyst adsorbs to the regions not covered with the resist (conductive circuit forming regions), as compared with the regions covered with the resist. Therefore, a portion of copper catalyst remains on the conductive circuit forming regions, without being completely removed with an alkaline permanganate solution. The copper catalyst is likely to be oxidized, so that a Pd catalyst is substituted for the copper catalyst by a substitution reaction with Pd ions. According to this technique, a copper catalyst is not present under the resist, so that the insulating property between circuits is enhanced.
Japanese Patent Application Laid-open No. Hei 6-69632 (hereinafter, referred to as xe2x80x9cthird prior art techniquexe2x80x9d) discloses a technique of partially removing Sn of catalyst cores (Pdxe2x80x94Sn) adsorbing to an insulating substrate, forming a plating resist, and forming conductive circuits by electroless copper plating. According to this technique, the insulating substrate is treated with a hydrochloric acid solution or the like so that the Pd concentration of the catalyst cores adsorbing to the insulating substrate becomes 1 to 10 xcexcg/cm2 and the Sn concentration thereof becomes 0.1 to 2 xcexcg/cm2, and the concentration of the catalyst cores under the plating resist is controlled, thereby preventing the insulation resistance between circuit lines from being degraded.
However, the above-mentioned first to third prior art techniques have the following problems.
(1) According to the first prior art technique, it is difficult to completely remove catalyst cores from the surface of the plating resist, which makes it difficult to avoid electroless copper deposition onto the surface of the plating resist.
(2) According to the second prior art technique, a copper catalyst in the circuit forming regions is also etched with an alkaline permanganate solution. Therefore, it is required to strictly control the treatment conditions of the alkaline permanganate solution, resulting in poor operability.
(3) According to the third prior art technique, Pd and Sn are present under the plating resist. Therefore, in the case where the line space is 100 xcexcm or less, the insulating property between circuits is degraded due to moisture absorption.
Thus, it is an object of the present invention to provide a process for producing a printed wiring board which overcomes the problem regarding the insulating property between circuits of a printed circuit board produced by the above-mentioned conventional full-additive processes.
A process for producing a printed wiring board of the present invention includes: a first step of forming first catalyst cores for electroless plating made of single metal particles on an insulating surface of a substrate; a second step of patterning a plating resist on the substrate; a third step of forming second catalyst cores for electroless plating made of alloy particles on the surface of the substrate where the plating resist is not formed; and a fourth step of forming conductive circuits made of an electroless plating film on the surfaces of the substrate where the first catalyst cores and the second catalyst cores are formed.
An electrical insulating property between conductive circuits formed in the fourth step is largely influenced by the concentration of the first catalyst cores on the surface of the substrate. In order to ensure reliability of the electrical insulating property between conductive circuits, the electrical insulation resistance between conductive circuits is required to be 109xcexa9 or more. The preferable concentration of the first catalyst cores on the surface of the insulating substrate is 4xc3x9710xe2x88x928 atomic mol/cm2 or less.
The lower the concentration of the first catalyst cores, the better the insulating property between conductive circuits. According to the present invention, the lower limit of the concentration of the first catalyst cores is set to 4.7xc3x9710xe2x88x929 atomic mol/cm2. The purpose of this is to provide the first catalyst cores between the plating resists, and to allow the first catalyst cores to promote the formation of the second catalyst cores between the plating resists in the third step. As the first catalyst cores, metal particles of palladium (Pd) or copper (cu) can be used.
In the case where the first catalyst cores are made of Pd particles, the Pd particles are formed by allowing palladium complex ions, in which palladium ions are bound by ligands such as ammonia, pyridine, pyridine-3-sulfonic acid, and 2-aminopyridine, to adsorb to a substrate, followed by reducing with a reducing agent such as dimethylamine borane, sodium borohydride, or the like. The number of ligands binding to one Pd ion is 2 to 4.
In the case where the first catalyst cores are made of Cu metal particles, the Cu metal particles are formed by allowing a copper metal colloid to adsorb to a substrate.
According to the present invention, as the second catalyst cores, palladiumxe2x80x94tin alloy particles are used. The palladiumxe2x80x94tin alloy particles are formed by bringing a substrate into contact with a catalyst solution containing a palladiumxe2x80x94tin mixed colloid. In order to suppress adsorption of the palladiumxe2x80x94tin alloy particles to a plating resist, the plating resist is treated with an aqueous solution containing an anionic surfactant before bringing the substrate into contact with the catalyst solution containing a palladiumxe2x80x94tin mixed colloid.
According to the process for producing a printed wiring board of the present invention, a fifth step may be included between the second and third steps, in which the first catalyst cores on the surface of the substrate where a plating resist is not formed are replaced by third catalyst cores having electroless plating catalyst performance by an ion substitution reaction. In this case, as the first catalyst cores, copper metal particles are used, and the copper metal particles can be replaced by the third catalyst cores made of more stable palladium, silver, and nickel metal particles by an ion substitution reaction.
According to the present invention, there is provided a process for producing a printed wiring board characterized in that catalyst cores are formed on the surface of an insulating substrate in a concentration of 4xc3x9710xe2x88x928 atomic mol/cm2 or less, a plating resist is patterned and treated with an anionic surfactant solution, and the insulating substrate is treated with a catalyst solution containing a palladiumxe2x80x94tin mixed colloid. By treating the plating resist with an anionic surfactant solution, adsorption of the palladiumxe2x80x94tin mixed colloid to the surface of the plating resist can be suppressed. Catalyst cores previously formed on the surface of the substrate that is exposed between the plating resists have a function of promoting adsorption of a palladiumxe2x80x94tin mixed colloid, and enhance the formation of an electroless plating film (electroless copper plating film) between the plating resists. By setting the concentration of the catalyst cores under the plating resist to 4xc3x9710xe2x88x928 atomic mol/cm2 or less, a high insulating property can also be held between conductive circuits.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.